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? semiconductor components industries, llc, 2012 december, 2012 ? rev. 0 1 publication order number: NCP1244/d NCP1244 fixed frequency current mode controller for flyback converters the NCP1244 is a new fixed ? frequency current ? mode controller featuring the dynamic self ? supply. this function greatly simplifies the design of the auxiliary supply and the v cc capacitor by activating the internal startup current source to supply the controller during start ? up, transients, latch, stand ? by etc. this device contains a special hv detector which detect the application unplug from the ac input line and triggers the x2 discharge current. it features a timer ? based fault detection that ensures the detection of overload and an adjustable compensation to help keep the maximum power independent of the input voltage. due to frequency foldback, the controller exhibits excellent efficiency in light load condition while still achieving very low standby power consumption. internal frequency jittering, ramp compensation, and a versatile latch input make this controller an excellent candidate for the robust power supply designs. a dedicated off mode allows to reach the extremely low no load input power consumption via ?sleeping? whole device and thus minimize the power consumption of the control circuitry. features ? fixed ? frequency current ? mode operation (65 khz and 100 khz frequency options) ? frequency foldback then skip mode for maximized performance in light load and standby conditions ? timer ? based overload protection with latched (option a) or auto ? recovery (option b) operation ? high ? voltage current source with dynamic self ? supply, simplifying the design of the v cc circuitry ? frequency modulation for softened emi signature ? adjustable overpower protection dependant on the bulk voltage ? latch ? off input combined with the overpower protection sensing input ? v cc operation up to 28 v, with overvoltage detection ? 500/800 ma source/sink drive peak current capability ? 10 ms soft ? start ? internal thermal shutdown ? no ? load standby power < 30 mw ? x2 capacitor in emi filter discharging feature ? these devices are pb ? free and halogen free/bfr free typical applications ? ac ? dc adapters for notebooks, lcd, and printers ? offline battery chargers ? consumer electronic power supplies ? auxiliary/housekeeping power supplies ? offline adapters for notebooks soic ? 7 case 751u marking diagram http://onsemi.com 44xff alywx 1 8 44xff = specific device code x = a or b ff = 65 or 100 a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 39 of this data sheet. ordering information 18 5 3 4 (top view) latch cs hv pin connections 6 2 fb gnd drv v cc free datasheet http:///
NCP1244 http://onsemi.com 2 typical application example figure 1. flyback converter application using the NCP1244 pin function description pin no pin name function pin description 1 latch latch ? off input pull the pin up or down to latch ? off the controller. an internal current source allows the direct connection of an ntc for over temperature detection. 2 fb feedback + shutdown pin an optocoupler collector to ground controls the output regulation. the part goes to the low consumption off mode if the fb input pin is pulled to gnd. 3 cs current sense this input senses the primary current for current ? mode operation, and offers an overpower compensation adjustment. 4 gnd ? the controller ground 5 drv drive output drives external mosfet 6 vcc vcc input this supply pin accepts up to 28 vdc, with overvoltage detection. the pin is connected to an external auxiliary voltage. it is not allowed to connect another circuit to this pin to keep low input power consumption. 8 hv high ? voltage pin connects to the rectified ac line to perform the functions of start ? up current source, self ? supply and x2 capacitor discharge function and the hv sensing for the overpower protection purposes. it is not allowed to connect this pin to dc voltage. free datasheet http:///
NCP1244 http://onsemi.com 3 simplified internal block schematic figure 2. simplified internal block schematic freq folback jittering vskip 0.7v skip_cmp skipb vramp_offset 1.4v 4umho ramp_ota csref division ratio 5 internal resitance 20k soft start timer reset q set qb clamp fault timer tsd latch management fb cs drv gnd vcc rfb1 fault ilimit_cmp rfb2 rfb3 vilim 0.7v faultb latchb pwm_cmp softstart_cmp leb 250ns leb 120ns csstop_cmp vcsstop 1.05v tsd latch enable reset ss_end ilimit vfb(reg) max_ton autorecovery timer reset q set qb pwm ic stop v to i iopc = 0.5u*(vhv ? 125) vfb(opc) 2.35v von off_mode_cmp1 icstart fbbuffer vhv sample 2.2v vcc uvlo_cmp vccoff 9.5v latch vccovp otp votp 0.8v vovp 2.5v otp_cmp ovp_cmp vclamp 1.2v rclamp 1k hv vccovp_cmp vccovp 26v intc vdd intc ss_end set q reset qb latch reset ovp ac_off uvlo vcc 5ua vcc_int ic stopb vhv sample sg & x2 & vcc vdd reg vdd vcc regulator poweronreset_cmp vcc(reg) vccreset 10.8v 5v control 15 ma dual hv start ? up current source icstartb tsd reset vfb < 1.5v fix current setpoint 300mv x2 discharge 10.8v regulator on_cmp stop_cmp vccon vccmin 12v 10.5v vccon vccmin gotooffmode timer 150ms set q reset qb 0.4v voff off_mode_cmp2 fm input osc 65khz pfm input square output saw output ton_max output 3.0v vdd 1ua +shv +shv 55 us filter 300 us filter 10 us filter free datasheet http:///
NCP1244 http://onsemi.com 4 maximum ratings rating symbol value unit drv (pin 5) maximum voltage on drv pin (dc ? current self ? limited if operated within the allowed range) (note 1) ?0.3 to 20 1000 (peak) v ma v cc (pin 6) v cc power supply voltage, v cc pin, continuous voltage power supply voltage, v cc pin, continuous voltage (note 1) ?0.3 to 28 30 (peak) v ma hv (pin 8) maximum voltage on hv pin (dc ? current self ? limited if operated within the allowed range) ?0.3 to 500 20 v ma v max maximum voltage on low power pins (except pin 5, pin 6 and pin 8) (dc ? current self ? limited if operated within the allowed range) (note 1) ?0.3 to 10 10 (peak) v ma r j ? a thermal resistance soic ? 7 junction-to-air, low conductivity pcb (note 2) junction-to-air, medium conductivity pcb (note 3) junction-to-air, high conductivity pcb (note 4) 162 147 115 c/w r j ? c thermal resistance junction ? to ? case 73 c/w t jmax operating junction temperature ? 40 to +150 c t strgmax storage temperature range ? 60 to +150 c esd capability, hbm model (all pins except hv) per jedec standard jesd22, method a114e > 2000 v esd capability, machine model per jedec standard jesd22, method a115a > 200 v esd capability, charged device model per jedec standard jesd22, method c101e > 1000 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains latch-up protection and exceeds 100 ma per jedec standard jesd78. 2. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51-1 conductivity test pcb. test conditions were under natural convection or zero air flow. 3. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 100 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51-2 conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 80 x 100 x 1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51-3 conductivity test pcb. test conditions were under natural convection or zero air flow. free datasheet http:///
NCP1244 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics test condition symbol min typ max unit high voltage current source minimum voltage for current source operation v hv(min) ? 30 40 v current flowing out of v cc pin v cc = 0 v v cc = v cc(on) ? 0.5 v i start1 i start2 0.2 5 0.5 8 0.8 11 ma off ? state leakage current v hv = 500 v, v cc = 15 v i start(off) 10 25 50 a off ? mode hv supply current v hv = 141 v, v hv = 325 v, v cc loaded by 4.7 f cap i hv(off) ? ? 45 50 60 70 a supply hv current source regulation threshold v cc(reg) 8 11 ? v turn ? on threshold level, v cc going up hv current source stop threshold v cc(on) 11.0 12.0 13.0 v hv current source restart threshold v cc(min) 9.5 10.5 11.5 v turn ? off threshold v cc(off) 8.5 8.9 9.3 v overvoltage threshold v cc(ovp) 25 26.5 28 v blanking duration on v cc(off) and v cc(ovp) detection t vcc(blank) ? 10 ? s v cc decreasing level at which the internal logic resets v cc(reset) 4.8 7.0 7.7 v v cc level for i start1 to i start2 transition v cc(inhibit) 0.2 0.8 1.25 v internal current consumption (note 5) drv open, v fb = 3 v, 65 khz drv open, v fb = 3 v, 100 khz cdrv = 1 nf, v fb = 3 v, 65 khz cdrv = 1 nf, v fb = 3 v, 100 khz off mode (skip or before start ? up) fault mode (fault or latch) i cc 1 i cc 1 i cc 2 i cc 2 i cc3 i cc4 1.3 1.3 1.8 2.3 0.67 0.3 1.85 1.85 2.6 2.9 0.9 0.6 2.2 2.2 3.0 3.5 1.13 0.9 ma x2 discharge comparator hysteresis observed at hv pin v hv(hyst) 1.5 3.5 5 v hv signal sampling period t sample ? 1.0 ? ms timer duration for no line detection t det 21 32 43 ms discharge timer duration t dis 21 32 43 ms oscillator oscillator frequency f osc 58 87 65 100 72 109 khz maximum on time for t j = 25 c to +125 c only f osc = 65 khz f osc = 100 khz t onmax(65khz) t onmax(100khz) 11.5 7.5 12.3 8.0 13.1 8.5 s maximum on time f osc = 65 khz f osc = 100 khz t onmax(65khz) t onmax(100khz) 11.3 7.4 12.3 8.0 13.1 8.5 s maximum duty cycle (corresponding to maximum on time at maximum switching frequency) f osc = 65 khz f osc = 100 khz d max ? 80 ? % 5. internal supply current only, currents sourced via fb pin is not included (current is flowing in gnd pin only). 6. guaranteed by design. 7. cs pin source current is a sum of i bias and i opc , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. free datasheet http:///
NCP1244 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics unit max typ min symbol test condition oscillator frequency jittering amplitude, in percentage of f osc a jitter 4 6 8 % frequency jittering modulation frequency f jitter 85 125 165 hz frequency foldback feedback voltage threshold below which frequency foldback starts v fb(folds) 1.8 2.0 2.2 v feedback voltage threshold below which frequency foldback is complete v fb(folde) 0.8 0.9 1.0 v minimum switching frequency v fb = v skip(in) + 0.1 f osc(min) 23 27 32 khz output driver rise time, 10 to 90% of v cc v cc = v cc(min) + 0.2 v, c drv = 1 nf t rise ? 40 70 ns fall time, 90 to 10% of v cc v cc = v cc(min) + 0.2 v, c drv = 1 nf t fall ? 40 70 ns current capability v cc = v cc(min) + 0.2 v, c drv = 1 nf drv high, v drv = 0 v drv low, v drv = v cc i drv(source) i drv(sink) ? ? 500 800 ? ? ma clamping voltage (maximum gate voltage) v cc = v ccmax ? 0.2 v, drv high, r drv = 33 k , c load = 220 pf v drv(clamp) 11 13.5 16 v high ? state voltage drop v cc = v cc(min) + 0.2 v, r drv = 33 k , drv high v drv(drop) ? ? 1 v current sense input pull ? up current v cs = 0.7 v i bias ? 1 ? a maximum internal current setpoint v fb > 3.5 v v ilim 0.66 0.70 0.74 v propagation delay from v ilimit detection to drv off v cs = v ilim t delay ? 80 110 ns leading edge blanking duration for v ilim t leb 200 250 320 ns threshold for immediate fault protection activation v cs(stop) 0.95 1.05 1.15 v leading edge blanking duration for v cs(stop) (note 6) t bcs 90 120 150 ns soft ? start duration from 1 st pulse to v cs = v ilim t sstart 8 11 14 ms frozen current setpoint v i(freeze) 275 300 325 mv internal slope compensation slope of the compensation ramp s comp(65khz) s comp(100khz) ? ? ? 32.5 ? 50 ? ? mv / s feedback internal pull ? up resistor t j = 25 c r fb(up) 15 20 25 k v fb to internal current setpoint division ratio k fb 4.7 5 5.3 ? internal pull ? up voltage on the fb pin (note 6) v fb(ref) 4.5 5 5.5 v feedback voltage below which the peak current is frozen v fb(freeze) 1.35 1.5 1.65 v 5. internal supply current only, currents sourced via fb pin is not included (current is flowing in gnd pin only). 6. guaranteed by design. 7. cs pin source current is a sum of i bias and i opc , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. free datasheet http:///
NCP1244 http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) characteristics unit max typ min symbol test condition skip cycle mode feedback voltage thresholds for skip mode v fb going down v fb going up v skip(in) v skip(out) 0.63 0.72 0.70 0.80 0.77 0.88 v remote control on fb pin the voltage above which the part enters the on mode v cc > v cc(off) , v hv = 60 v v on ? 2.2 ? v the voltage below which the part enters the off mode v cc > v cc(off) v off 0.35 0.40 0.45 v minimum hysteresis between the v on and v off v cc > v cc(off) , v hv = 60 v v hyst 500 ? ? mv pull ? up current in off mode v cc > v cc(off) i off ? 5 ? a go to off mode timer v cc > v cc(off) t gtom 500 600 700 ms overload protection fault timer duration t fault 108 128 178 ms autorecovery mode latch ? off time duration t autorec 0.85 1.00 1.35 s overpower protection v hv to i opc conversion ratio k opc ? 0.54 ? a / v current flowing out of cs pin (note 7) v hv = 125 v v hv = 162 v v hv = 325 v v hv = 365 v i opc(125) i opc(162) i opc(325) i opc(365) ? ? ? 105 0 20 110 130 ? ? ? 150 a fb voltage above which i opc is applied v hv = 365 v v fb(opcf) 2.12 2.35 2.58 v fb voltage below which is no i opc applied v hv = 365 v v fb(opce) ? 2.15 ? v latch ? off input high threshold v latch going up v ovp 2.35 2.5 2.65 v low threshold v latch going down v otp 0.76 0.8 0.84 v current source for direct ntc connection during normal operation during soft ? start v latch = 0 v i ntc i ntc(sstart) 65 130 95 190 105 210 a blanking duration on high latch detection 65 khz version 100 khz version t latch(ovp) 35 20 50 35 70 50 s blanking duration on low latch detection t latch(otp) ? 350 ? s clamping voltage i latch = 0 ma i latch = 1 ma v clamp0(latch) v clamp1(latch) 1.0 1.8 1.2 2.4 1.4 3.0 v temperature shutdown temperature shutdown t j going up t tsd ? 150 ? c temperature shutdown hysteresis t j going down t tsd(hys) ? 30 ? c 5. internal supply current only, currents sourced via fb pin is not included (current is flowing in gnd pin only). 6. guaranteed by design. 7. cs pin source current is a sum of i bias and i opc , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. free datasheet http:///
NCP1244 http://onsemi.com 8 typical characteristic 20 22 24 26 28 30 32 34 36 38 40 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) figure 3. minimum current source operation v hv(min) v hv(min) (v) 20 22 24 26 28 30 32 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) figure 4. off ? state leakage current i start(off) i start(off) ( a) 20 25 30 35 40 45 50 temperature ( c) figure 5. off ? mode hv supply current i hv(off) i hv(off) ( a) ? 50 ? 25 0 25 50 75 100 125 i hv(off) @ v hv = 325 v i hv(off) @ v hv = 141 v 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 temperature ( c) figure 6. high voltage startup current flowing out of v cc pin i start2 ? 50 ? 25 0 25 50 75 100 125 i start2 (ma) 0.65 0.66 0.67 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 temperature ( c) figure 7. maximum internal current setpoint v ilim v ilim (v) ? 50 ? 25 0 25 50 75 100 125 290 292 294 296 298 300 302 304 306 308 310 temperature ( c) figure 8. frozen current setpoint v i(freeze) for the light load operation v i(freeze) (mv) ? 50 ? 25 0 25 50 75 100 125 free datasheet http:///
NCP1244 http://onsemi.com 9 typical characteristic 0.95 0.97 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 1.15 temperature ( c) figure 9. threshold for immediate fault protection activation v cs(stop) v cs(stop) (v) ? 50 ? 25 0 25 50 75 100 125 40 50 60 70 80 90 100 110 temperature ( c) figure 10. propagation delay t delay t delay (ns) ? 50 ? 25 0 25 50 75 100 125 200 210 220 230 240 250 260 270 280 290 300 temperature ( c) figure 11. leading edge blanking duaration t leb t leb (ns) ? 50 ? 25 0 25 50 75 100 125 100 105 110 115 120 125 130 temperature ( c) figure 12. maximum overpower compensating current i opc(365) flowing out of cs pin i opc(365) ( a) ? 50 ? 25 0 25 50 75 100 125 15 16 17 18 19 20 21 22 23 24 temperature ( c) figure 13. fb pin internal pull ? up resistor r fb(up) r fb(up) (k ) ? 50 ? 25 0 25 50 75 100 125 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 temperature ( c) figure 14. fb pin open voltage v fb(ref) v fb(ref) (v) ? 50 ? 25 0 25 50 75 100 125 free datasheet http:///
NCP1244 http://onsemi.com 10 typical characteristic 2.35 2.40 2.45 2.50 2.55 2.60 2.65 temperature ( c) figure 15. latch pin high threshold v ovp v ovp (v) ? 50 ? 25 0 25 50 75 100 125 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 temperature ( c) figure 16. latch pin low threshold v otp v otp (v) ? 50 ? 25 0 25 50 75 100 125 70 75 80 85 90 95 100 105 110 temperature ( c) figure 17. current i ntc sourced from the latch pin, allowing direct ntc connection i ntc ( a) ? 50 ? 25 0 25 50 75 100 125 140 150 160 170 180 190 200 210 220 temperature ( c) figure 18. current i ntc(sstart) sourced from the latch pin, during soft ? start i ntc(sstart) ( a) ? 50 ? 25 0 25 50 75 100 125 60 61 62 63 64 65 66 67 68 69 70 temperature ( c) figure 19. oscillator f osc for the 65 khz version f osc (khz) ? 50 ? 25 0 25 50 75 100 125 90 91 92 93 94 95 96 97 98 99 100 figure 20. oscillator f osc for the 100 khz version f osc (khz) ? 50 ? 25 0 25 50 75 100 125 temperature ( c) free datasheet http:///
NCP1244 http://onsemi.com 11 typical characteristic 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 temperature ( c) figure 21. maximum on time t onmax for the 65 khz version t onmax ( s) ? 50 ? 25 0 25 50 75 100 125 7.8 7.9 8.0 8.1 8.2 8.3 8.4 t onmax ( s) temperature ( c) figure 22. maximum on time t onmax for the 100 khz version ? 50 ? 25 0 25 50 75 100 125 75 76 77 78 79 80 81 82 83 84 85 temperature ( c) figure 23. maximum duty ratio d max d max (%) ? 50 ? 25 0 25 50 75 100 125 22 23 24 25 26 27 28 29 30 f osc(min) ( s) temperature ( c) figure 24. minimum switching frequency f osc(min) ? 50 ? 25 0 25 50 75 100 125 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 temperature ( c) figure 25. fb pin voltage below which frequency foldback starts v fb(folds) v fb(folds) (v) ? 50 ? 25 0 25 50 75 100 125 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 temperature ( c) figure 26. fb pin voltage below which frequency foldback complete v fb(folde) v fb(folde) (v) ? 50 ? 25 0 25 50 75 100 125 free datasheet http:///
NCP1244 http://onsemi.com 12 typical characteristic 0.63 0.65 0.67 0.69 0.71 0.73 0.75 0.77 temperature ( c) figure 27. fb pin skip ? in level v skip(in) v skip(in) (v) ? 50 ? 25 0 25 50 75 100 125 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86 0.88 temperature ( c) figure 28. fb pin skip ? out level v skip(out) v skip(on) (v) ? 50 ? 25 0 25 50 75 100 125 figure 29. fb pin level v fb(opcf) above which is the overpower compensation applied 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 temperature ( c) v fb(opcf) (v) ? 50 ? 25 0 25 50 75 100 125 figure 30. fb pin level v fb(opce) below which is no overpower compensation applied v fb(opce) (v) temperature ( c) 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 ? 50 ? 25 0 25 50 75 100 125 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 figure 31. v cc turn ? on threshold level, v cc going up hv current source stop threshold v cc(on) v cc(on) (v) temperature ( c) ? 50 ? 25 0 25 50 75 100 125 9.5 9.7 9.9 10.1 10.3 10.5 10.7 10.9 11.1 11.3 11.5 ? 50 ? 25 0 25 50 75 100 125 figure 32. hv current source restart threshold v cc(min) v cc(min) (v) temperature ( c) free datasheet http:///
NCP1244 http://onsemi.com 13 typical characteristic 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 figure 33. v cc turn ? off threshold (uvlo) v cc(off) v cc(off) (v) temperature ( c) ? 50 ? 25 0 25 50 75 100 125 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 ? 50 ? 25 0 25 50 75 100 125 figure 34. v cc decreasing level at which the internal logic resets v cc(reset) v cc(reset) (v) temperature ( c) 1.7 1.7 1.8 1.8 1.9 1.9 2.0 figure 35. internal current consumption when drv pin is unloaded i cc1 (ma) temperature ( c) ? 50 ? 25 0 25 50 75 100 125 i cc1(100khz) i cc1(65khz) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 i cc2 (ma) figure 36. internal current consumption when drv pin is loaded by 1 nf temperature ( c) i cc2(100khz) i cc2(65khz) ? 50 ? 25 0 25 50 75 100 125 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 figure 37. x2 discharge comparator hysteresis observed at hv pin v hv(hyst) v hv(hyst) (v) temperature ( c) ? 50 ? 25 0 25 50 75 100 125 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 ? 50 ? 25 0 25 50 75 100 125 figure 38. hv signal sampling period t sample temperature ( c) t sample (ms) free datasheet http:///
NCP1244 http://onsemi.com 14 typical characteristic 2.2 2.3 2.3 2.4 2.4 2.5 2.5 2.6 2.6 ? 50 ? 25 0 25 50 75 100 125 figure 39. fb pin voltage level above which is entered on mode v on v on (v) temperature ( c) 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 ? 50 ? 25 0 25 50 75 100 125 figure 40. fb pin voltage level below which is entered off mode v off v off (v) temperature ( c) 120 125 130 135 140 145 150 ? 50 ? 25 0 25 50 75 100 125 figure 41. fault timer duration t fault t fault (ms) temperature ( c) 100 120 140 160 180 200 220 240 260 280 300 ? 50 ? 25 0 25 50 75 100 125 figure 42. go to off mode timer duration t gtom t gtom (ms) temperature ( c) free datasheet http:///
NCP1244 http://onsemi.com 15 application information functional description the NCP1244 includes all necessary features to build a safe and efficient power supply based on a fixed ? frequency flyback converter. the NCP1244 is a multimode controller as illustrated in figure 43. the mode of operation depends upon line and load condition. under all modes of operation, the NCP1244 terminates the drv signal based on the switch current. thus, the NCP1244 always operates in current mode control so that the power mosfet current is always limited. under normal operating conditions, the fb pin commands the operating mode of the NCP1244 at the voltage thresholds shown in figure 43. at normal rated operating loads (from 100% to approximately 33% full rated power) the NCP1244 controls the converter in fixed frequency pwm mode. it can operate in the continuous conduction mode (ccm) or discontinuous conduction mode (dcm) depending upon the input voltage and loading conditions. if the controller is used in ccm with a wide input voltage range, the duty ? ratio may increase up to 50%. the build ? in slope compensation prevents the appearance of sub ? harmonic oscillations in this operating area. for loads that are between approximately 32% and 10% of full rated power, the converter operates in frequency foldback mode (ffm). if the feedback pin voltage is lower than 1.5 v the peak switch current is kept constant and the output voltage is regulated by modulating the switching frequency for a given and fixed input voltage v hv . effectively, operation in ffm results in the application of constant volt ? seconds to the flyback transformer each switching cycle. voltage regulation in ffm is achieved by varying the switching frequency in the range from 65 khz (or 100 khz) to 27 khz. for extremely light loads (below approximately 6% full rated power), the converter is controlled using bursts of 27 khz pulses. this mode is called as skip mode. the ffm, keeping constant peak current and skip mode allows design of the power supplies with increased efficiency under the light loading conditions. keep in mind that the aforementioned boundaries of steady ? state operation are approximate because they are subject to converter design parameters. figure 43. mode control with fb pin voltage v fb 3.5 v 2.2 v 2.0 v 1.5v 1.1 v 0.8 v 0.7 v 0.4 v ffm pwm at f osc fixed i peak skip mode 0 v low consumption off mode off on there was implemented the low consumption off mode allowing to reach extremely low no load input power. this mode is controlled by the fb pin and allows the remote control (or secondary side control) of the power supply shut ? down. most of the device internal circuitry is unbiased in the low consumption off mode. only the fb pin control circuitry and x2 cap dischar ging circuitry is operating in the low consumption off mode. if the voltage at feedback pin decreases below the 0.4 v the controller will enter the low consumption off mode. the controller can start if the fb pin voltage increases above the 2.2 v level. see the detailed status diagrams for the both versions fully latched a and the autorecovery b on the following figures. the basic status of the device after wake?up by the v cc is the off mode and mode is used for the overheating protection mode if the thermal shutdown protection is activated. free datasheet http:///
NCP1244 http://onsemi.com 16 figure 44. operating status diagram for the fully latched version a of the device extra low consumption power on reset latch=0 off mode latch=x latch latch=1 stop reset latch=0 tsd tsd soft start running skip mode skip in skip out ssend efficient operating mode dynamic self ? supply (if not enoughgh auxiliary voltage is present) regulated self ? supply x2 cap discharge latch=0 no ac (v fb < v off ) * gtomtimer*(v cc > v ccoff ) v cc < v ccreset v cc > v ccreset (v fb > v on ) * latch (v fb > v on )*latch v cc < v ccreset (v cc > v ccon )*s hv v cc < v ccoff v ilim * t fault v hv > v hv(min) ovp+otp+v ccovp +v csstop free datasheet http:///
NCP1244 http://onsemi.com 17 figure 45. operating status diagram for the autorecovery version b of the device extra low consumption power on reset latch=0 autorec=0 x2 cap discharge latch=0 autorec=0 off mode latch=x autorec=x latch latch=1 stop reset latch=0 autorec=0 autorecovery latch autorec=1 tsd tsd soft start running skip mode skip in skip out ssend efficient operating mode regulated self ? supply dynamic self ? supply (if not enoughgh auxiliary voltage is present) no ac v cc < v ccreset v cc > v ccreset (v fb > v on ) * latch (v fb > v on )*latch * autorec (v fb < v off ) * gtomtimer*(v cc > v ccoff ) (v cc > v ccon )*s hv v cc < v ccoff v ilim * t fault ovp+otp+v ccovp v cc < v ccreset (v fb > v on ) * autorec v csstop t autorec v hv > v hv(min) free datasheet http:///
NCP1244 http://onsemi.com 18 the information about the fault (permanent latch or autorecovery) is kept during the low consumption off mode due the safety reason. the reason is not to allow unlatch the device by the remote control being in off mode. start ? up of the controller at start ? up, the current source turns on when the voltage on the hv pin is higher than v hv(min) , and turns off when v cc reaches v cc(on) , then turns on again when v cc reaches v cc(min) , until v cc is supplied by an external source. the controller actually starts the first time v cc reaches v cc(on) when the slope on hv pin is positive. even though the dynamic self ? supply is able to maintain the v cc voltage between v cc(on) and v cc(min) by turning the hv start ? up current source on and off, it can only be used in light load condition, otherwise the power dissipation on the die would be too much. as a result, an auxiliary voltage source is needed to supply v cc during normal operation. the dynamic self ? supply is useful to keep the controller alive when no switching pulses are delivered, e.g. in latch or fault condition, or to prevent the controller from stopping during load transients when the v cc might drop. the NCP1244 accepts a supply voltage as high as 28 v, with an overvoltage threshold v cc(ovp) that latches the controller off. figure 46. v cc start ? up timing diagram time v hv time v cc time drv v hv(start) v hv(min) v cc(on) v cc(min) hv current source = i start1 hv current source = i start2 waits next v cc(on) before starting v cc(inhibit) free datasheet http:///
NCP1244 http://onsemi.com 19 for safety reasons, the start ? up current is lowered when v cc is below v cc(inhibit) , to reduce the power dissipation in case the v cc pin is shorted to gnd (in case of v cc capacitor failure, or external pull ? down on v cc to disable the controller). there is only one condition for which the current source doesn?t turn on when v cc reaches v cc(inhibit) : the voltage on hv pin is too low (below v hv(min) ). the controller can restart only when vcc reaches vcc(on) and when the slope on hv pin is positive during the short ac line drop ? outs. this feature differentiates between the short ac line drop ? outs and application plug off. the minimum positive slope is defined by the equation 1 in following chapter. time output time v cc time drv v cc(on) v cc(min) controller stops at v cc(off) loss of regulation when v hv is too low time v hv ac line drop ? out switching restarts at v cc(on) and positive s hv v cc(off) v cc charges up when v hv is high enough v out hv pin slope s hv is positive figure 47. ac line drop ? out timing diagram free datasheet http:///
NCP1244 http://onsemi.com 20 x2 cap discharge feature the x2 capacitor discharging feature is offered by usage of the NCP1244. this feature save approx. 16 mw ? 25 mw input power depending on the emi filter x2 capacitors volume and it saves the external components count as well. the discharge feature is ensured via the start ? up current source with a dedicated control circuitry for this function. the x2 capacitors are being discharged by current defined as i start2 when this need is detected. there is used a dedicated structure called ac line unplug detector inside the x2 capacitor discharge control circuitry. see the figure 48 for the block diagram for this structure and figures 49, 50 and 52 for the timing diagrams. the basic idea of ac line unplug detector lies in comparison of the direct sample of the high voltage obtained via the high voltage sensing structure with the delayed sample of the high voltage. the delayed signal is created by the sample & hold structure. the comparator used for the comparison of these signals is without hysteresis inside. the resolution between the slopes of the ac signal and dc signal is defined by the sampling time t sample and additional internal offset n os . these parameters ensure the noise immunity as well. the additional offset is added to the picture of the sampled hv signal and its analog sum is stored in the c 1 storage capacitor. if the voltage level of the hv sensing structure output crosses this level the comparator cmp output signal resets the detection timer and no dc signal is detected. the additional offset n os can be measured as the v hv(hyst) on the hv pin. if the comparator output produces pulses it means that the slope of input signal is higher than set resolution level and the slope is positive. if the comparator output produces the low level it means that the slope of input signal is lower than set resolution level or the slope is negative. there is used the detection timer which is reset by any edge of the comparator output. it means if no edge comes before the timer elapses there is present only dc signal or signal with the small ac ripple at the hv pin. this type of the ac detector detects only the positive slope, which fulfils the requirements for the ac line presence detection. in case of the dc signal presence on the high voltage input, the direct sample of the high voltage obtained via the high voltage sensing structure and the delayed sample of the high voltage are equivalent and the comparator produces the low level signal during the presence of this signal. no edges are present at the output of the comparator, that?s why the detection timer is not reset and dc detect signal appears. the minimum detectable slope by this ac detector is given by the ration between the maximum hysteresis observed at hv pin v hv(hyst),max and the sampling time: s min v hv(hyst),max t sample (eq. 1) than it can be derived the relationship between the minimum detectable slope and the amplitude and frequency of the sinusoidal input voltage: v max v hv(hyst),max 2 f t sample 5 2 35 1 10 ? 3 (eq. 2) 22.7 v the minimum detectable ac rms voltage is 16 v at frequency 35 hz, if the maximum hysteresis is 5 v and sampling time is 1 ms. the x2 capacitor discharge feature is available in any controller operation mode to ensure this safety feature. the detection timer is reused for the time limiting of the discharge phase, to protect the device against overheating. the discharging process is cyclic and continues until the ac line is detected again or the voltage across the x2 capacitor is lower than v hv(min ). this feature ensures to discharge quite big x2 capacitors used in the input line filter to the safe level. it is important to note that it is not allowed to connect hv pin to any dc voltage due this feature. e.g. directly to bulk capacitor. during the hv sensing or x2 cap discharging the v cc net is kept above the v cc(off) voltage by the self ? supply in any mode of device operation to supply the control circuitry. during the discharge sequence device runs normally. free datasheet http:///
NCP1244 http://onsemi.com 21 figure 48. the ac line unplug detector structure used for x2 capacitor discharge system figure 49. the ac line unplug detector timing diagram free datasheet http:///
NCP1244 http://onsemi.com 22 figure 50. the ac line unplug detector timing diagram detail with noise effects free datasheet http:///
NCP1244 http://onsemi.com 23 figure 51. hv pin ac input timing diagram with x2 capacitor discharge sequence when the application is unplugged under extremely low line condition free datasheet http:///
NCP1244 http://onsemi.com 24 figure 52. hv pin ac input timing diagram with x2 capacitor discharge sequence when the application is unplugged under high line and heavy load condition free datasheet http:///
NCP1244 http://onsemi.com 25 time v hv time one shot time drv t det time x2 discharge current t dis x2 discharge ac line unplug x2 capacitor discharge ac line unplug detector starts t det t dis x2 capacitor discharge no ac detection x2 discharge starts only at v cc(on) drv pulses stops when v cc < v cc(off) figure 53. hv pin ac input timing diagram with x2 capacitor discharge sequence when the application is unplugged under high line and light load condition the low consumption off mode there was implemented the low consumption off mode allowing to reach extremely low no load input power as described in previous chapters. if the voltage at feedback pin decreases below the 0.4 v the controller enters the off mode. the internal v cc is turned ? off, the ic consumes extremely low v cc current and only the voltage at external v cc capacitor is maintained by the self ? supply circuit. the self ? supply circuit keeps the v cc voltage at the v cc(reg) level. the supply for the fb pin watch dog circuitry and fb pin bias is provided via the low consumption current sources from the external v cc capacitor. the controller can only start, if the fb pin voltage increases above the 2.2 v level. see figure 54 for timing diagrams. only the x2 cap discharge and self ? supply features is enabled in the low consumption off mode. the x2 cap discharging feature is enable due the safety reasons and the self ? supply is enabled to keep the v cc supply, but only very low v cc consumption appears in this mode. any other features are disabled in this mode. the information about the latch status of the device is kept in the low consumption off mode and this mode is used for the tsd protection as well. the protection timer gotooffmode t gtom is used to protect the application against the false activation of the low consumption off mode by the fast drop outs of the fb pin voltage below the 0.4 v level. e.g. in case when is present high fb pin voltage ripple during the skip mode. free datasheet http:///
NCP1244 http://onsemi.com 26 figure 54. start ? up, shutdown and ac line unplug time diagram oscillator with maximum on time and frequency jittering the NCP1244 includes an oscillator that sets the switching frequency 65 khz or 100 khz depending on the version. the maximum on time is 12.3 s (for 65 khz version) or 8 s (for 100 khz version) with an accuracy of 7%. the maximum on time corresponds to maximum duty cycle of the drv pin is 80% at full switching frequency. in order to improve the emi signature, the switching frequency jitters 6 % around its nominal value, with a triangle ? wave shape and at a frequency of 125 hz. this frequency jittering is active even when the frequency is decreased to improve the efficiency in light load condition. figure 55. frequency modulation of the maximum switching frequency free datasheet http:///
NCP1244 http://onsemi.com 27 low load operation modes: frequency foldback mode (ffm) and skip mode in order to improve the efficiency in light load conditions, the frequency of the internal oscillator is linearly reduced from its nominal value down to f osc(min) . this frequency foldback starts when the voltage on fb pin goes below v fb(folds) , and is complete when v fb reaches v fb(folde) . the maximum on ? time duration control is kept during the frequency foldback mode to provide the natural transformer core anti ? saturation protection. the frequency jittering is still active while the oscillator frequency decreases as well. the current setpoint is fixed to 300 mv in the frequency foldback mode if the feedback voltage de creases below the v fb(freeze) level. this feature increases efficiency under the light loads conditions as well. figure 56. frequency foldback mode characteristic figure 57. current setpoint dependency on the feedback pin voltage when the fb voltage reaches v skip(in) while decreasing, skip mode is activated: the driver stops, and the internal consumption of the controller is decreased. while v fb is below v skip(out) , the controller remains in this state; but as soon as v fb crosses the skip out threshold, the drv pin starts to pulse again. free datasheet http:///
NCP1244 http://onsemi.com 28 figure 58. skip mode timing diagram clamped driver the supply voltage for the NCP1244 can be as high as 28 v, but most of the mosfets that will be connected to the drv pin cannot accept more than 20 v on their gate. the driver pin is therefore clamped safely below 16 v. this driver has a typical capability of 500 ma for source current and 800 ma for sink current. current ? mode control with slope compensation and soft ? start NCP1244 is a current ? mode controller, which means that the fb voltage sets the peak current flowing in the inductance and the mosfet. this is done through a pwm comparator: the current is sensed across a resistor and the resulting voltage is applied to the cs pin. it is applied to one input of the pwm comparator through a 250 ns leb block. on the other input the fb voltage divided by 5 sets the threshold: when the voltage ramp reaches this threshold, the output driver is turned off. the maximum value for the current sense is 0.7 v, and it is set by a dedicated comparator. each time the controller is starting, i.e. the controller was off and starts ? or restarts ? when v cc reaches v cc(on) , a soft ? start is applied: the current sense setpoint is increased by 15 discrete steps from 0 (the minimum level can be higher than 0 because of the leb and propagation delay) until it reaches v ilim (after a duration of t sstart ), or until the fb loop imposes a setpoint lower than the one imposed by the soft ? start (the two comparators outputs are or?ed). free datasheet http:///
NCP1244 http://onsemi.com 29 figure 59. soft ? start feature under some conditions, like a winding short ? circuit for instance, not all the energy stored during the on time is transferred to the output during the off time, even if the on time duration is at its minimum (imposed by the propagation delay of the detector added to the leb duration). as a result, the current sense voltage keeps on increasing above v ilim , because the controller is blind during the leb blanking time. dangerously high current can grow in the system if nothing is done to stop the controller. that?s what the additional comparator, that senses when the current sense voltage on cs pin reaches v cs(stop) ( = 1.5 x v ilim ), does: as soon as this comparator toggles, the controller immediately enters the protection mode. in order to allow the NCP1244 to operate in ccm with a duty cycle above 50%, the fixed slope compensation is internally applied to the current ? mode control. the slope appearing on the internal voltage setpoint for the pwm comparator is ? 32.5 mv/ s typical for the 65 khz version, and ? 50 mv/ s for the 100 khz version. the slope compensation can be observable as a value of the peak current at cs pin. the internal slope compensation circuitry uses a sawtooth signal synchronized with the internal oscillator is subtracted from the fb voltage divided by k fb . free datasheet http:///
NCP1244 http://onsemi.com 30 figure 60. slope compensation block diagram figure 61. slope compensation timing diagram internal overpower protection the power delivered by a flyback power supply is proportional to the square of the peak current in discontinuous conduction mode: p out 1 2 l p f sw i p 2 (eq. 3) unfortunately, due to the inherent propagation delay of the logic, the actual peak current is higher at high input voltage than at low input voltage, leading to a significant difference in the maximum output power delivered by the power supply. free datasheet http:///
NCP1244 http://onsemi.com 31 figure 62. needs for line compensation for true overpower protection to compensate this and have an accurate overpower protection, an offset proportional to the input voltage is added on the cs signal by turning on an internal current source: by adding an external resistor in series between the sense resistor and the cs pin, a voltage offset is created across it by the current. the compensation can be adjusted by changing the value of the resistor. but this offset is unwanted to appear when the current sense signal is small, i.e. in light load conditions, where it would be in the same order of magnitude. therefore the compensation current is only added when the fb voltage is higher than v fb(opce) . however, because the hv pin can be connected to an ac voltage, there is needed an additional circuitry to read or at least closely estimate the actual voltage on the bulk capacitor. figure 63. overpower protection current relation to feedback voltage free datasheet http:///
NCP1244 http://onsemi.com 32 figure 64. overpower protection current relation to peak of rectified input line ac voltage figure 65. block schematic of overpower protection circuit free datasheet http:///
NCP1244 http://onsemi.com 33 a 3 bit a/d converter with the peak detector senses the ac input, and its output is periodically sampled and reset, in order to follow closely the input voltage variations. the sample and reset events are given by the output from the ac line unplug detector . the sensed hv pin voltage peak value is validated when no hv edges from comparator are present after last falling edge during two sample clocks. see figure 66 for details. overcurrent protection with fault timer the overload protection depends only on the current sensing signal, making it able to work with any transformer, even with very poor coupling or high leakage inductance. when an overcurrent occurs on the output of the power supply, the fb loop asks for more power than the controller can deliver, and the cs setpoint reaches v ilim . when this event occurs, an internal t fault timer is started: once the timer times out, drv pulses are stopped and the controller is either latched off (latched protection, option a) or this latch can be released in autorecovery mode (option b), the controller tries to restart after t autorec . another possibility of the latch release is the v cc power on reset or the ac line unplug event detected via ac detector. therefore the latch can be released by the end of the 1 st x2 discharge event. the timer is reset when the cs setpoint goes back below v ilim before the timer elapses. the fault timer is also started if the driver signal is reset by the max duty ? ratio. the controller also enters the same protection mode if the voltage on the cs pin reaches 1.5 times the maximum internal setpoint v cs(stop) (allows to detect winding short ? circuits) or there appears low v cc supply. see figures 67 and 68 for the timing diagram. in autorecovery mode if the fault has gone, the supply resumes operation; if not, the system starts a new burst cycle. free datasheet http:///
NCP1244 http://onsemi.com 34 figure 66. overpower compensation timing diagram free datasheet http:///
NCP1244 http://onsemi.com 35 protection modes and the latch mode releases event timer protection next device status release to normal operation mode overcurrent v ilim > 0.7 v fault timer latch autorecovery ? b version 1 st x2 discharge event v cc < v cc(reset) winding short v sense > v cs(stop) immediate reaction latch autorecovery ? b version 1 st x2 discharge event v cc < v cc(reset) low supply v cc < v cc(off) 10 s timer latch 1 st x2 discharge event v cc v cc(reset) external otp, ovp 55 s (35 s at 100 khz) latch 1 st x2 discharge event v cc < v cc(on) high supply v cc > v cc(ovp) 10 s timer latch 1 st x2 discharge event v cc < v cc(reset) internal tsd 10 s timer device stops, hv start ? up current source stops (v cc > v cc(on) ) & tsdb off mode v fb < v off 600 ms timer device stops and internal v cc is turned off (v cc > v cc(on) ) & ( v fb > v on ) free datasheet http:///
NCP1244 http://onsemi.com 36 v cc(on) v cc(min) figure 67. latched timer ? based overcurrent protection (option a) free datasheet http:///
NCP1244 http://onsemi.com 37 figure 68. timer ? based protection mode with autorecovery release from latch ? off (option b) v cc(on) v cc(min) free datasheet http:///
NCP1244 http://onsemi.com 38 latch ? off input figure 69. latch detection schematic the latch pin is dedicated to the latch ? off function: it includes two levels of detection that define a working window, between a high latch and a low latch: within these two thresholds, the controller is allowed to run, but as soon as either the low or the high threshold is crossed, the controller is latched off. the lower threshold is intended to be used with an ntc thermistor, thanks to an internal current source i ntc . an active clamp prevents the voltage from reaching the high threshold if it is only pulled up by the i ntc current. to reach the high threshold, the pull ? up current has to be higher than the pull ? down capability of the clamp (typically 1.5 ma at v ovp ). to avoid any false triggering, spikes shorter than 50 s (for the high latch and 65 khz version) or 350 s (for the low latch) are blanked and only longer signals can actually latch the controller. reset occurs the v cc is cycled down to a reset voltage, which in a real application can only happen if the power supply is unplugged from the ac line. upon startup, the internal references take some time before being at their nominal values; so one of the comparators could toggle even if it should not. therefore the internal logic does not take the latch signal into account before the controller is ready to start: once v cc reaches v cc(on) , the latch pin high latch state is taken into account and the drv switching starts only if it is allowed; whereas the low latch (typically sensing an over temperature) is taken into account only after the soft ? start is finished. in addition, the ntc current is doubled to i ntc(sstart) during the soft ? start period, to speed up the charging of the latch pin capacitor. the maximum value of latch pin capacitor is given by the following formula (the standard start ? up condition is considered and the ntc current is neglected): c latch max t sstart min i ntc(sstart) min v clamp0 min 8.0 10 ? 3 130 10 ? 6 1.0 f 1.04 f (eq. 4) free datasheet http:///
NCP1244 http://onsemi.com 39 figure 70. latch timing diagram v cc(on) v cc(min) temperature shutdown the NCP1244 includes a temperature shutdown protection with a trip point typically at 150 c and the typical hysteresis of 30 c. when the temperature rises above the high threshold, the controller stops switching instantaneously, and goes to the off mode with extremely low power consumption. there is kept the v cc supply to keep the tsd information. when the temperature falls below the low threshold, the start ? up of the device is enabled again, and a regular start ? up sequence takes place. see the status diagrams at the figures 44 and 45. ordering information 5 ordering part no. overload protection switching frequency package shipping ? NCP1244ad065r2g latched 65 khz soic ? 7 (pb ? free) 2500 / tape & reel NCP1244bd065r2g autorecovery 65 khz soic ? 7 (pb ? free) 2500 / tape & reel NCP1244ad100r2g latched 100 khz soic ? 7 (pb ? free) 2500 / tape & reel NCP1244bd100r2g autorecovery 100 khz soic ? 7 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. free datasheet http:///
NCP1244 http://onsemi.com 40 package dimensions soic ? 7 case 751u issue e seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? a ? ? b ? g m b m 0.25 (0.010) ? t ? b m 0.25 (0.010) t s a s m 7 pl 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP1244/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative free datasheet http:///

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